The present invention relates to a semiconductor device, in which delay of a gate used for, for example, a high-speed transistor, a very high-speed memory, etc. is reduced, and relates to a producing method of such a semiconductor device.
Conventionally, a gate electrode of a MOS transistor or the like and a wiring layer over the gate electrode are connected via a connecting hole which is formed in an interlayer insulating film on the gate electrode.
In the above arrangement, after the interlayer insulating film is formed on the gate electrode formed on a semiconductor substrate and the connecting hole is made in the interlayer insulating film, the wiring layer, for example, is deposited thereon.
However, as a semiconductor device is highly integrated and a semiconductor element is made minute in recent years, an area of the connecting hole has a tendency to be decreased. Moreover, as a semiconductor element is highly integrated, a wiring layer is being multi-layered, and thus a thickness of an interlayer insulating film has a tendency to become thicker in order to smooth unevenness due to the multi-layered wiring layer. For this reason, a depth of the connecting hole becomes deeper, and thus it is very difficult to sufficiently deposit an electrically conductive material composing a wiring layer in a connecting hole with a small area and with a deep depth.
On the contrary, a method of depositing an electrically conductive electrode material with high coverage and low resistance into a connecting hole and connecting a gate electrode to a wiring layer via the electrically conductive electrode material has been proposed.
However, this method possibly influences a driving speed of a transistor, for example, and thus possibly reduces a high-speed operation of the transistor because resistance of a buried electrode, connecting resistance between the buried electrode and the gate electrode, and connecting resistance between the buried electrode and the wiring layer are added to resistance of the gate electrode.
The resistance added to the gate electrode possibly increases a delay in driving a word line of a non-volatile semiconductor memory or the like. For this reason, the number of memory cells, which can be connected to one word line which is connected to a circuit for controlling word lines such as a word line decoder, is limited.
Further, in the case the connecting hole is made on the gate electrode by using a patterning technique, it is necessary to provide an aligning margin in patterning between the gate electrode and the connecting hole, and thus it is difficult to make an element minute.
As mentioned above, in accordance with the conventional semiconductor device and the producing method thereof, it is difficult to reduce the resistance between the gate electrode and the wiring layer formed on the gate electrode and to make an element minute.